G. H. RAISONI COLLEGE OF ENGINEERING Digdoh Hills, Hingna Road, Nagpur-16. Department of Computer Science & Engg. Question Bank Session 2011-12 Year/Branch/Sem/Sec : 3rd/CSE/ B Subject: Computer Architecture & Organization ____________________________________________________________ _______________ UNIT 1. 1. Explain the three major design levels in a computer system. 2. What are the different standard steps in register level design ? 3. Describe in detail the components which are generally used to design register level circuits. 1. What are the different levels of design ?
Discuss with suitable example. 2. How performance evaluation is done using simulation technique ? 3. Explain processor level components. 4. Explain the performance parameters for a computer system . 5. What are the different functional units of basic computer system ? 6. Compare different bus system for connection between CPU , Memory and I/O Devices. 1. Explain prototype structure , performance measurement and queuing Model steps of processor level design . UNIT 2. 1. How the following cases are interpreted in floating point format ; a) Not a number b) Overflow ) -00 d) +00 1. Explain restoring and non-restoring algorithms for integer division. 2. What is an overflow ? How is it detected ? 3. Explain with suitable examples the need for the following addressing Modes ; a) Index b) Indirect c) Autoincrement d) Autodecrement 1. Explain the concept for Booth’s multiplication algorithm . 2. Derive an algorithm in flowchart form for restoring & non-restoring method of integer division and apply both algorithms for 10/3 division. 1.
Explain the IEEE standard floating point format and represent decimal numbers in this format ; i) -0. 000125 ii) 3. 92*102 1. Explain in brief bit sliced ALU. 1. Suppose that the hex content of two CPU registers in a 32-bit processor are as follows : Ro = 0 1 2 3 7 6 5 4 R1 = 7 6 5 4 E D C B The following store word instructions are executed to transfer the contents Of these registers to main memory M. STORE Ro,ADR STORE R1,ADR+4 Assuming that M is byte addressable give the content of all memory locations affected by the above code . ) If the computer is Big-endian and b) If the computer is Little-endian 1. Explain base register and index addressing mode . What are the advantages of using these addressing modes ? 1. Solve the multiplication by using Booth’s algorithm : Multiply -13 with +12, 13 x -6 1. Describe IEEE standard floating point number format . 2. Using non-restoring division method solve the following ; 9/4 3. Give the set of instructions required to execute the following statement for two address processes . X = (A +B)*(C+D) 1.
Develop Booth’s algorithm for multiplying binary integers in signed 2’s complement representation . Show step by step multiplication process using this algorithm when the following numbers are multiplied ; -15 x 13 UNIT 3. 1. What are advantages and disadvantages of hardwired method of control unit design. Explain any one method of hardwired control unit design . 1. Write a brief note on microprogramming . What are the ways to increase the speed in microprogramming ? 1. Explain delay element method and sequence counter method of control unit design in brief . . Draw and explain microprogrammed control unit . 2. What is micro-program sequencing ? 3. Explain how emulation facilities transition into a new system with a minimum disruption . 1. write short notes on :- i) Instruction formats in computer Architecture ii) Combinational array multipliers iii) Coprocessors iv) Emulation v) Bit ORing Technique 1. What was Wilke’s original proposal for microprogrammed control unit Design ? 1. Compare the two approaches of control unit design. 2.
Compare Horizontal and Vertical microinstruction formats . 3. Explain sequence counter method of hardwired control unit . 4. Write in short about the differences between hardwired control and Microprogrammed control . UNIT 4. 1. What is memory mapping ? Discuss in detail 2. Draw and explain virtual memory organization . 3. What is virtual memory ? Explain with neat sketch address translation in Virtual memory system. 4. Explain the concept of the following ; i) Cache memory ii) Content addressable memory iii) Memory Interleaving v) Bus contention 5. Give design of 64 x 8 memory with 16K x 1 static RAM chips . 6. What is the purpose of Translation lookaside buffer ? 7. Write short note on replacement algorithms. 8. What is the difference between CPU controlled memory access and direct memory access . 1. Explain in detail address mapping techniques used in Cache memory giving suitable example of each . 1. Describe virtual memory system and explain the concept of locality of reference. 2. Design a 4K x 8bits RAM using 1K x 2 bits RAM ICs. 3.
Explain the following with reference to cache memory : i) Locality of reference ii) Mapping techniques iii) Delayed write iv) Dirty / Modified bit 1. Explain Random , Semi-random and serial access modes of memory. 2. What is TLB ? Why is it used ? 3. With reference to virtual memory explain the following : i) Paging ii) Replacement algorithm iii) Virtual address and physical address 1. Write short note on associative memory. 2.
What do you mean by replacement policy ? What are the different Categories of it ? Explain. 18. Give the structure of a typical static RAM cell. UNIT 5. 1. 1. Write in brief about problems faced in local computer communication . 2. 2. Write short notes on ; i) Interrupt driven I/O ii) DMA controlled I/O iii) Programmed I/O 1. 3. Write a note on bus arbitration techniques . 2. 4. What are the interrupts ? Explain vectored interrupt. 3. 5. Explain Daisy chain priority interrupt scheme for interrupt handling. 4. 6.
What are the factors that determine whether communication system is a LAN , WAN or MAN. 1. 7. Distinguish between local and long distance communication methods. 2. 8. Explain the terms : i) Seek and access time ii) Latency time 1. 9. What is mean by bus contention ? Discuss the various bus arbitration methods with their advantages and disadvantages. 10. Write in brief about problems faced in local computer communication. UNIT 6. 1. 1. Explain various schemes that can be used in an instruction pipeline in order to minimize the performance degradation caused by instruction branching. . 2. Give an example of a program that will cause data conflict in four stage Instruction pipeline . List the techniques to deal with data conflict. 1. 3. Write in brief about Flynn’s classification of parallel processing. 2. 4. Write short note on ; i) Vector processor ii) RISC processor iii) Pipelining iv) I/O Processor 1. 5. Explain in detail loosely and tightly coupled multiprocessor structures. 2. 6. Explain two major types of pipelines . Explain